*request the AHA3520 product specification for complete details. comtech aha corporation comtech aha corporation product brief* AHA3520 20 mbytes/sec aldc data compression coprocessor ic the AHA3520 is a single-chip cmos lossless compression and decompression integrated circuit. the device implements the aldc compression algorithm defined by various industry standards. this algorithm is also known as adaptive lossless data compression. the device compresses, decompresses or passes data through. flexible interface connects directly with various microprocessors and dma devices used in tape drive systems. content addressable memory within the aldc engine eliminates external sram s typically required for dictionary storage in a compression system. other system features includ e compatibility to an aldc1-20s-ha device. features performance: ? 20 mbytes/sec data compression, decompression or pass-through rate ? 2 to 1 average compression ratio ? multiple byte transfers without microprocessor intervention ? error checking in decomp ression mode reportable via an interrupt flexibility: ? in-line or look-aside system architectures supported ? polled or interrupt driven i/o ? two independent dma ports programmable for 8 or 16-bit transfers and handshaking modes system interface: ? single-chip data compression solution ? programmable interrupts ? interfaces directly with industry standard scsi chips others: ? industry standard aldc adaptive lossless compression algorithm ? complies to qic-154, ecma 222, ansi x3.280-1996 and iso 15200 standard specifications ? compatible to aldc1-20s-ha specification ? 100 pin package in 14 mm 20 mm pqfp ? rohs compliant applications ? tape drives ? printers and copiers 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 aae vdd gnd bdata[7] bdata[6] bdata[5] bdata[4] bdata[3] bdata[2] vdd gnd bdata[1] baf bae bdata[0] bdata[15] bdata[14] bdata[13] bdata[12] vdd gnd bdata[11] bdata[10] bdata[9] bdata[8] bparity[0] bparity[1] vdd gnd ireqn aparity[1] gnd vdd aparity[0] adata[8] adata[9] adata[10] adata[11] adata[12] gnd vdd adata[13] adata[14] adata[15] adata[0] adata[1] apcs ard adata[2] gnd vdd adata[3] adata[4] adata[5] testn2 adata[6] adata[7] gnd vdd acin addr[0] addr[1] addr[2] testn1 gnd bcin testn0 addr[3] addr[4] vdd gnd clk tristaten resetn bcout bwr brd waitn bpcs ireq mdata[7] testn3 testn4 mdata[6] mdata[5] mdata[4] mdata[3] acout awr gnd vdd mcin[0] mcin[1] mdata[2] mdata[1] mdata[0] aaf mmode testn5 testn6 AHA3520a-040 pqc-g yywwd - country of origin lllll note: yywwd = date code; lllll = lot number
comtech aha corporation figure 1: AHA3520 block diagram functional description major blocks in this device are the microprocessor interface, port a interface, port b interface, and the compression/decompression engine. the microprocessor interface provides status and control inform ation by register access. port a and port b interfaces are dma ports configurable for bus widt h, polarity, handshaking modes, and other options. the operating mode establishes the direction of both the port a and port b interfaces. compression or compression pass through sets the port a interface as an input and the port b interface as an output. conversely decompression or decomp ression pass through sets the port a interface as an output and the port b interface as an input. decompression output disabled mode allows the device to decompress a block of data up to a predetermined point while dumping the uncompressed da ta, then automatically begin outputting the remain ing uncompressed data in that block or record. a four byte transfer size counter allows the user to partition the data into blocks of four gigabytes or less to process. compression pass through mode and decompression pass through modes allow data transfers through the device without changing the data. both the port a interface and port b inte rface have a 16-byte fifo with almost empty and almost full signal pins and programmable thresh olds. both of the dma interfaces, port a and port b, have programmable wait states in addition to four selectable dma transfer modes: asynchronous request/acknowledge pair, asynchronous burst mode, and two peripheral access modes that correlate with the two microprocessor modes. port b transfer counter port a dma state port a transfer counter machine clock generation port b dma state machine interrupt logic processor interface state machine pass through controller processor interface aldc engine aparity[1:0] adata[15:0] clock mdata[7:0] port a interface port b interface AHA3520 compression chip acout ard apcs aaf bparity[1:0] bdata[15:0] bcout bcin bpcs baf mcin[1:0] waitn addr[4:0] mmode resetn ireqn ireq awr acin aae bae brd bwr
comtech aha corporation the aldc compression algorithm the aldc (adaptive lossless data compression) algorithm is one variant of the lz1 (lempel-ziv 1) class of data compression algorithms, first proposed by abraham lempel and jacob ziv in 1977. lz1 algorithms achieve compression by building and maintaining a data structure, called a historybuffer. an lz1 encode process and an lz1 decode process both initialize this structure to the same known state, and update it in an identical fashion. the encoder does th is using the input data it receives for compressio n, while the decoder generates an identical data stream as its output, which it also uses for the update process. the compression process consists of examining the incoming data stream to identify any sequences or strings of data bytes which already exist in the encoder history. if an identical such history is available to a decoder, this matching string can be encoded and output as a 2 element copypointer, containing a byte count and history location. it is then possible for a decoder to reproduce this string exactly, by copying it from the given location in its own history. if the copypointer can be enc oded in fewer bits of information than required for the data string it specifies, compression is achieved. if an incoming byte of data does not form part of a matching string, a literal, containing this embedded value, is encoded and then output to explicitly represent this byte. a decoder performs the inverse operation by first parsing a compressed data stream into literals and copypointers for processing. aldc is a lossless algor ithm, insuring that the decompressed data output is exactly the same as the uncompressed data inpu t. qic-154 development standard describes this industry standard algorithm in detail. port a and port b configuration port a and port b operate identically. they both are 16-bit bidirectional da ta ports with parity checking and generation. there are three configuration registers associated with each port and a polarity register that determines the polarity of all of the control signals for that port. the function of the control pin is determined by either xcnf0[13, 12] bits or command register programmed for peripheral access. the polarity of control signals are controlled by specific bits in the polarity registers. table 1: port a interface signals table 2: port b interface signals signal name master slave=0 slave slave=1 apol bit direction acin dacka dreqa 7 i acout dreqa dacka 5 o awr deasserted awr 4 o ard deasserted ard 3 o apcs apcs apcs 2 o aaf aaf aaf 1 o aae aae aae 0 o signal name master slave=0 slave slave=1 bpol bit direction bcin dackb dreqb 7 i bcout dreqb dackb 5 o bwr deasserted bwr 4 o brd deasserted brd 3 o bpcs bpcs bpcs 2 o baf baf baf 1 o bae bae bae 0 o
comtech aha corporation pb3520_1205 comtech aha corporation fax: 208.892.5601 tel: 208.892.5600 e-mail: sales@aha.com www.aha.com moscow id 83843-8331 a subsidiary of comtech te lecommunications corporation 1126 alturas drive moscow id 83843-8331 1126 alturas drive systems applications a typical application fo r the AHA3520 is the implementation of data compression in a tape drive system. an in-line architecture is employed in this system. the in-line application inserts compression directly between the host and the system data buffer. there is no direct connection between the buffer and the host. for compress ion, data flows from the host, through the bus controller and into the AHA3520. the data is then compressed by the aldc engine and flows in to the system buffer followed by the tape drive interface. this data flow is usually controlled by a local microprocessor. for decompression, the flow is reversed. in an in-line architecture the aha compression chip operates at the data rate of the host interface controller. the AHA3520 device supports a sustained data transfer rate of up to 20 mbytes/sec. in a look-aside applicatio n, the system buffer is in series with the data flow. there is a direct connection between the host and the buffer memory through a dma port. for co mpression, data flows from the host, through the bus interface and peripheral controller and into the system buffer. data then flows from the system buffer into the AHA3520 where it is compressed and sent back to the system buffer. finally, data is transferred from the system buffer interface . during decompression, this flow is reversed. example in-line application example look-aside application ordering information about aha comtech aha corporation (aha) develops and markets superior integrated circuits, boards, and intellectual property core technology for communications systems architects worldwide. aha has been setting the st andard in forward error correction and lossless data compression technology for many year s and provides flexible, cost-effective solutions for today?s growing bandwidth and reliability challenges. comtech aha corporation is a who lly owned subsidiary of comtech telecommuncations corp. (nasdaq: cmtl). for more informa tion, visit www.aha.com. AHA3520 data compression interface chip bus scsi or atapi controller buffer dram system processor system memory controller tape drive interface AHA3520 data compression interface chip bus scsi or atapi controller buffer dram system processor system memory controller peripheral controller data flow control part number description AHA3520a-040 pqc-g 20 mbytes/sec aldc data compression coprocessor ic
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